functional block diagram buried zener ref comp- arator analog in db7 v cc v ss digital common convert int clock 8-bit sar db6 db5 db4 db3 db2 db1 db0 msb lsb analog common bipolar offset control data ready ad673 5k data enable 8-bit current output dac rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 8-bit a/d converter ad673 features complete 8-bit a/d converter with reference, clock and comparator 30 m s maximum conversion time full 8- or 16-bit microprocessor bus interface unipolar and bipolar inputs no missing codes over temperature operates on +5 v and C12 v to C15 v supplies mil-std-883 compliant version available general description the ad673 is a complete 8-bit successive approximation analog-to-digital converter consisting of a dac, voltage refer- ence, clock, comparator, successive approximation register (sar) and 3-state output buffersall fabricated on a single chip. no external components are required to perform a full ac- curacy 8-bit conversion in 20 m s. the ad673 incorporates advanced integrated circuit design and processing technologies. the successive approximation function is implemented with i 2 l (integrated injection logic). laser trim- ming of the high stability sicr thin-film resistor ladder network insures high accuracy, which is maintained with a temperature compensated sub-surface zener reference. operating on supplies of +5 v and C12 v to C15 v, the ad673 will accept analog inputs of 0 v to +10 v or C5 v to +5 v. the trailing edge of a positive pulse on the convert line initiates the 20 m s conversion cycle. data ready indicates comple- tion of the conversion. the ad673 is available in two versions. the ad673j as speci- fied over the 0 c to +70 c temperature range and the ad673s guarantees 1/2 lsb relative accuracy and no missing codes from C55 c to +125 c. two package configurations are offered. all versions are also of- fered in a 20-pin hermetically sealed ceramic dip. the ad673j is also available in a 20-pin plastic dip. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 product highlights 1. the ad673 is a complete 8-bit a/d converter. no external components are required to perform a conversion. 2. the ad673 interfaces to many popular microprocessors without external buffers or peripheral interface adapters. 3. the device offers true 8-bit accuracy and exhibits no missing codes over its entire operating temperature range. 4. the ad673 adapts to either unipolar (0 v to +10 v) or bipolar (C5 v to +5 v) analog inputs by simply grounding or opening a single pin. 5. performance is guaranteed with +5 v and C12 v or C15 v supplies. 6. the ad673 is available in a version compliant with mil- std-883. refer to the analog devices military products databook or current ad673/883b data sheet for detailed specifications.
ad673especifications ad673j ad673s model min typ max min typ max units resolution 8 8 bits relative accuracy, l 6 1/2 6 1/2 lsb t a = t min to t max 6 1/2 6 1/2 lsb full-scale calibration 2 2 2 lsb unipolar offset 6 1/2 6 1/2 lsb bipolar offset 6 1/2 6 1/2 lsb differential nonlinearity, 3 88 bits t a = t min to t max 88 bits temperature range 0 +70 e55 +125 c temperature coefficients unipolar offset 6 1 6 1 lsb bipolar offset 6 1 6 1 lsb full-scale calibration 2 6 2 6 2 lsb power supply rejection positive supply +4.5 v+ +5.5 v 6 2 6 2 lsb negative supply e15.75 v ve e14.25 v 6 2 6 2 lsb e12.6 v ve e11.4 v 6 2 6 2 lsb analog input impedance 3.0 5.0 7.0 3.0 5.0 7.0 k w analog input ranges unipolar 0 +10 0 +10 v bipolar e5 +5 e5 +5 v output coding unipolar positive true binary positive true binary bipolar positive true offset binary positive true offset binary logic output output sink current (v out = 0.4 v max, t min to t max ) 3.2 3.2 ma output source current 4 (v out = 2.4 v min, t min to t max ) 0.5 0.5 ma output leakage 6 40 6 40 m a logic inputs input current 6 100 6 100 m a logic 1 2.0 2.0 v logic 0 0.8 0.8 v conversion time, t a and t min to t max 10 20 30 10 20 30 m s power supply v+ +4.5 +5.0 +7.0 +4.5 +5.0 +7.0 v ve e11.4 e15 e16.5 e11.4 e15 e16.5 v operating current v+ 15 20 15 20 ma ve 9 15 9 15 ma notes 1 relative accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the zero to the full scale of the device. 2 full-scale calibration is guaranteed trimmable to zero with an external 200 w potentiometer in place of the 15 w fixed resistor. full scale is defined as 10 volts minus 1 lsb, or 9.961 v. 3 defined as the resolution for which no missing codes will occur. 4 the data output lines have active pull-ups to source 0 5 ma. the data ready line is open collector with a nominal 6 k w internal pull-up resistor. specifications subject to change without notice. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. (t a = +25 8 c, v+ = +5 v, ve = e12 v or e15 v, all voltages measured with respect to digital common, unless otherwise noted) rev. a e2e
ad673 rev. a e3e ordering guide temperature relative model range accuracy package option 1 ad673jn 0 c to +70 c 1/2 lsb max plastic dip (n-20) ad673jd 0 c to +70 c 1/2 lsb max ceramic dip (d-20) ad673sd 2 e55 c to +125 c 1/2 lsb max ceramic dip (d-20) ad673jp 0 c to +70 c 1/2 lsb max plcc (p-20a) notes 1 d = ceramic dip; n = plastic dip; p = plastic leaded chip carrier. 2 for details on grade and package offering screened in accordance with mil-std-883, refer to the analog devices military products databook . absolute maximum ratings v+ to digital common . . . . . . . . . . . . . . . . . . . . . 0 v to +7 v ve to digital common . . . . . . . . . . . . . . . . . . . 0 v to e16.5 v analog common to digital common . . . . . . . . . . . . . . . 1 v analog input to analog common . . . . . . . . . . . . . . . . . 15 v control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to v+ digital outputs (high impedance state) . . . . . . . . . . 0 v to v+ power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mw functional description a block diagram of the ad673 is shown in figure 1. the posi- tive convert pulse must be at least 500 ns wide. dr goes high within 1.5 m s after the leading edge of the convert pulse in- dicating that the internal logic has been reset. the negative edge of the convert pulse initiates the conversion. the internal 8-bit current output dac is sequenced by the integrated injec- tion logic (i 2 l) successive approximation register (sar) from its most significant bit to least significant bit to provide an output current which accurately balances the input signal current through the 5 k w resistor. the comparator determines whether the addition of each successively weighted bit current causes the dac current sum to be greater or less than the input current; if the sum is more, the bit is turned off. after testing all bits, the sar contains a 8-bit binary code which accurately represents the input signal to within (0.05% of full scale). buried zener ref comp- arator analog in db7 v+ ve digital common convert int clock 8-bit sar db6 db5 db4 db3 db2 db1 db0 msb lsb analog common bipolar offset control data ready ad673 5k data enable 8-bit current output dac figure 1. ad673 functional block diagram the sar drives dr low to indicate that the conversion is com- plete and that the data is available to the output buffers. data enable can then be activated to enable the 8-bits of data de- sired. data enable should be brought high prior to the next conversion to place the output buffers in the high impedance state. the temperature compensated buried zener reference provides the primary voltage reference to the dac and ensures excellent stability with both time and temperature. the bipolar offset in- put controls a switch which allows the positive bipolar offset current (exactly equal to the value of the msb less 1/2 lsb) to be injected into the summing (+) node of the comparator to off- set the dac output. thus the nominal 0 v to +10 v unipolar input range becomes a e5 v to +5 v range. the 5 k w thin-film input resistor is trimmed so that with a full-scale input signal, an input current will be generated which exactly matches the dac output with all bits on. unipolar connection the ad673 contains all the active components required to per- form a complete a/d conversion. thus, for many applications, all that is necessary is connection of the power supplies (+5 v and e12 v to e15 v), the analog input and the convert pulse. however, there are some features and special connections which should be considered for achieving optimum performance. the functional pinout is shown in figure 2. the standard unipolar 0 v to +10 v range is obtained by short- ing the bipolar offset control pin (pin 16) to digital common (pin 17). 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad673 * pins 1 & 2 are internally connected to test points and should be left floating nc * digital common data ready nc data enable nc * lsb db0 db1 analog in analog common bipolar offset db2 db3 db4 db5 db6 msb db7 v+ convert ve pin 1 identifier figure 2. ad673 pin connections
ad673 rev. a e4e full-scale calibration the 5 k w thin-film input resistor is laser trimmed to produce a current which matches the full-scale current of the internal dac-plus about 0.3%?when an analog input voltage of 9.961 volts (10 volts e 1 lsb) is applied at the input. the input resis- tor is trimmed in this way so that if a fine trimming potentio- meter is inserted in series with the input signal, the input current at the full scale input voltage can be trimmed down to match the dac full-scale current as precisely as desired. how- ever, for many applications the nominal 9.961 volt full scale can be achieved to sufficient accuracy by simply inserting a 15 w re- sistor in series with the analog input to pin 14. typical full-scale calibration error will then be within 2 lsb or 0.8%. if more precise calibration is desired, a 200 w trimmer should be used instead. set the analog input at 9.961 volts, and set the trimmer so that the output code is just at the transition between 111111 10 and 11111111. each lsb will then have a weight of 39.06 mv. if a nominal full scale of 10.24 volts is desired (which makes the lsb have a weight of exactly 40.0 mv), a 100 w resistor and a 100 w trimmer (or a 200 w trimmer with good resolution) should be used. of course, larger full-scale ranges can be arranged by using a larger input resistor, but lin- earity and full-scale temperature coefficient may be compro- mised if the external resistor becomes a sizeable percentage of 5 k w figure 3 illustrates the connections required for full-scale calibration. figure 3. standard ad673 connections unipolar offset calibration since the unipolar offset is less than 1/2 lsb for all versions of the ad673, most applications will not require trimming. fig- ure 4 illustrates two trimming methods which can be used if greater accuracy is necessary. figure 4a shows how the converter zero may be offset to correct for initial offset and/or input signal offsets. as shown, the circuit gives approximately symmetrical adjustment in unipolar mode. figure 5 shows the nominal transfer curve near zero for an ad673 in unipolar mode. the code transitions are at the edges of the nominal bit weights. in some applications it will be prefer- able to offset the code transitions so that they fall between the nominal bit weights, as shown in the offset characteristics. figure 5. ad673 transfer curve?unipolar operation (approximate bit weights shown for illustration, nominal bit weights % 39.06 mv) this offset can easily be accomplished as shown in figure 4b. at balance (after a conversion) approximately 2 ma flows into the analog common terminal. a 10 w resistor in series with this terminal will result in approximately the desired l/2 bit offset of the transfer characteristics. the nominal 2 ma analog common current is not closely controlled in manufacture. if high accuracy is required, a 20 w potentiometer (connected as a rheostat) can be used as r1. additional negative offset range may be obtained by using larger values of r1. of course, if the zero transition point is changed, the full-scale transition point will also move. thus, if an offset of 1/2 lsb is introduced, full scale trimming as described on the previous page should be done with an analog input of 9.941 volts. note: during a conversion, transient currents from the analog common terminal will disturb the offset voltage. capacitive decoupling should not be used around the offset network. these transients will settle appropriately during a conversion. capaci- tive decoupling will pump up and fail to settle resulting in conversion errors. power supply decoupling, which returns to analog signal common, should go to the signal input side of the resistive offset network. figure 4. unipolar offset trimming figure 4a. figure 4b.
ad673 rev. a e5e bipolar connection to obtain the bipolar e5 v to +5 v range with an offset binary output code, the bipolar offset control pin is left open. a e5.00 volt signal will give a 8-bit code of 00000000; an input of 0.00 volts results in an output code of 10000000 and +4.961 volts at the input yields the 11111111 code. the nominal trans- fer curve is shown in figure 6. figure 6. ad673 transfer curve?bipolar operation note that in the bipolar mode, the code transitions are offset 1/4 lsb such that an input voltage of 0 volts e5 mv to +35 mv yields the code representing zero (10000000). each output code is then centered on its nominal input voltage. full-scale calibration full-scale calibration is accomplished in the same manner as in unipolar operation except the full-scale input voltage is +4.61 volts. negative full-scale calibration the circuit in figure 4a can also be used in bipolar operation to offset the input voltage (nominally C5 v) which results in the 000000 00 code. r2 should be omitted to obtain a symmetrical range. the bipolar offset control input is not directly ttl compatible but a ttl interface for logic control can be constructed as shown in figure 7. figure 7. bipolar offset controlled by logic gate gate output = 1 unipolar 0 vC10 v input range gate output = 0 bipolar 5 v input range sample-hold amplifier connection to the ad673 many situations in high-speed acquisition systems or digitizing rapidly changing signals require a sample-hold amplifier (sha) in front of the a-d converter. the sha can acquire and hold a signal faster than the converter can perform a conversion. a sha can also be used to accurately define the exact point in time at which the signal is sampled. for the ad673, a sha can also serve as a high input impedance buffer. figure 8 shows the ad673 connected to the ad582 monolithic sha for high speed signal acquisition. in this configuration, the ad582 will acquire a 10 volt signal in less than 10 m s with a droop rate less than 100 m v/ms. dr goes high after the conversion is initiated to indicate that re- set of the sar is complete. in figure 8 it is also used to put the ad582 into the hold mode while the ad673 begins its conver- sion cycle. (the ad582 settles to final value well in advance of the first comparator decision inside the ad673). dr goes low when the conversion is complete placing the ad582 back in the sample mode. configured as shown in fig- ure 8, the next conversion can be initiated after a 10 m s delay to allow for signal acquisition by the ad582. observe carefully the ground, supply, and bypass capacitor con- nections between the two devices. this will minimize ground noise and interference during the conversion cycle. figure 8. sample-hold interface to the ad673
ad673 rev. a e6e grounding considerations the ad673 provides separate analog and digital common connections. the circuit will operate properly with as much as 200 mv of common-mode voltage between the two commons. this permits more flexible control of system common bussing and digital and analog returns. in normal operation, the analog common terminal may gener- ate transient currents of up to 2 ma during a conversion. in ad- dition a static current of about 2 ma will flow into analog common in the unipolar mode after a conversion is complete. the analog common current will be modulated by the varia- tions in input signal. the absolute maximum voltage rating between the two com- mons is 1 volt. it is recommended that a parallel pair of back-to-back protection diodes be connected between the commons if they are not connected locally. control and timing of the ad673 the operation of the ad673 is controlled by two inputs: con- vert and data enable . starting a conversion the conversion cycle is initiated by a positive-going convert pulse at least 500 ns wide. the rising edge of this pulse resets the internal logic, clears the result of the previous conversion, and sets dr high. the falling edge of convert begins the conversion cycle. when conversion is completed dr returns low. during the conversion cycle, de should be held high. if de goes low during a conversion, the data output buffers will be enabled and intermediate conversion results will be present on the data output pins. this may cause bus conflicts if other de- vices in a system are trying to use the bus. t cs t dsc v oh + v ol 2 v ih + v il 2 t c convert dr figure 9. convert timing reading the data the three-state data output buffers is enabled by de . access time of these buffers is typically 150 ns (250 maximum). the data outputs remain valid until 50 ns after the enable signal re- turns high, and are completely into the high-impedance state 100 ns later. v ih + v il 2 de t hd t dd v oh v ol data valid t hl high impedance high impedance db0edb7 figure 10. read timing timing specifications parameter symbol min typ max units convert pulse width t cs 500 ? ? ns dr delay from convert t dsc ? 1 1.5 m s conversion time t c 10 20 30 m s data access time t dd 0 150 250 ns data valid after de high t hd 50 ? ? ns output float delay t hl ? 100 200 ns microprocessor interface considerations? general when an analog-to-digital converter like the ad673 is inter- faced to a microprocessor, several details of the interface must be considered. first, a signal to start the converter must be gen- erated; then an appropriate delay period must be allowed to pass before valid conversion data may be read. in most applications, the ad673 can interface to a microprocessor system with little or no external logic. the most popular control signal configuration consists of de- coding the address assigned to the ad673, then gating this sig- nal with the system?s wr signal to generate the convert pulse, and gating it with rd to enable the output buffers. the use of a memory address and memory wr and rd signals de- notes memory-mapped i/o interfacing, while the use of a separate i/o address space denotes isolated i/o interfacing. figure 11 shows a generalized diagram of the control logic for an ad673 interfaced to an 8-bit data bus, where an address adc addr has been decoded. adc addr starts the con- verter when written to (the actual data being written to the con- verter does not matter) and contains the high byte data during read operations. figure 11. g eneral ad673 interface to 8-bit microprocessor
ad673 rev. a e7e in systems where this read-write interface is used, at least 30 microseconds (the maximum conversion time) must be al- lowed to pass between starting a conversion and reading the re- sults. this delay or time-out period can be implemented in a short software routine such as a countdown loop, enough dummy instructions to consume 30 microseconds, or enough actual useful instructions to consume the required time. in tightly- timed systems, the dr line may be read through an external three-state buffer to determine precisely when a conversion is complete. higher-speed systems may choose to use dr to signal an interrupt to the processor at the end of a conversion. figure 12. typical ad673 timing diagram convert pulse generation the ad673 is tested with a convert pulse width of 500 ns and will typically operate with a pulse as short as 300 ns. how- ever, some microprocessors produce active wr pulses which are shorter than this. either of the circuits shown in figure 13 can be used to generate an adequate convert pulse for the ad673. in both circuits, the short low-going wr pulse sets the convert line high through a flip-flop. the rising edge of dr (which signifies that the internal logic has been reset) resets the flip-flop and brings convert low, which starts the conversion. note that t dsc is slightly longer when the result of the previous conversion contains a logic 1 on the lsb. this means that the actual convert pulse generated by the circuits in figure 13 will vary slightly in width. figure 13a. using 74ls00 figure 13b. using 1/2 74ls74
ad673 rev. a e8e outline dimensions dimensions shown in inches and (mm). 20-pin ceramic dip (d-20) 20-pin plastic dip (n-20) c853ce5e3/87 printed in u.s.a.
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